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Abstract:

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In this study, a dual-mode Delta Sigma modulator for both ‎WLAN and GSM standards has been designed. In order to reduce the power consumption and to ‎optimize the chip area, a reconfigurable structure, which can be separately tuned for these two different ‎applications, is used. The proposed modulator is based on a multi-bit VCO instead of a conventional flash ‎quantizer. Due to the possibility of lower voltage application and lower power consumption, the VCO-‎based Delta Sigma modulator can be a good choice especially for sub-100nm technology, where the ‎performance of the analog circuits becomes limited, and conversely superior switching rates can be ‎achieved. The idea of VCO-based Delta Sigma converter has been recently developed, however the multi-‎mode reconfigurable structure is proposed and analyzed for the first time in this research. The proposed ‎modulator is dedicated to operate with the two major WLAN and GSM standards. It is designed at ‎system level in general, but the VCO part is implemented at transistor level using 180nm CMOS ‎technology. The simulations’ results show a saving of at least 86% of power consumption in the ‎VCO part, in the GSM standard compared to WLAN.‎

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Steady-state and transient response of the active power filter based on instantaneous power theory compensation method is dependent on the accurately and quickly extract the DC component of load active power. In this paper, for improving the response of this method, the numerical filter based on recursive least squares with variable forgetting factor in order to separation of DC component of load active power is proposed. Unlike conventional low-pass filters, the feature of designed numerical filter is independent of load harmonic components, quick and precision of the answer. Also, using wavelet transform the performance of active power filter under the non-ideal voltage condition is improved. Finally, the second order delta-sigma modulation is used to generate the switching pulses. Simulation results on MATLAB / SIMULINK software shows that the proposed method is properly.

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This paper presents a new circuit to configure power amplifier (PA) for return-to-zero on-off-keying (RZ-OOK) transmitters. The proposed PA works as a multimode structure with configurable data rate and output power. The programmable data rate function is achieved by duty cycle adjustment of input data and producing input RZ-data by a simple circuit, which leads to a linear scale of data rate with power consumption. This implies that any desired level of output power can be transmitted with different power consumption according to the power budget. The RZ-data is also utilized to perform the output power reconfiguration. The PA represents data rate of 0.3Mb/s to 3Mb/s and it can deliver output power level from -23dBm to 0dBm. During data rate adjustment, power consumption varies from 0.099mW to 0.99mW when the output power is 0dBm. Also, PA consumes 0.07mW to 0.99mW at the output power tuning range with a data rate of 3Mb/s.