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Abstract:

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In this study, a dual-mode Delta Sigma modulator for both ‎WLAN and GSM standards has been designed. In order to reduce the power consumption and to ‎optimize the chip area, a reconfigurable structure, which can be separately tuned for these two different ‎applications, is used. The proposed modulator is based on a multi-bit VCO instead of a conventional flash ‎quantizer. Due to the possibility of lower voltage application and lower power consumption, the VCO-‎based Delta Sigma modulator can be a good choice especially for sub-100nm technology, where the ‎performance of the analog circuits becomes limited, and conversely superior switching rates can be ‎achieved. The idea of VCO-based Delta Sigma converter has been recently developed, however the multi-‎mode reconfigurable structure is proposed and analyzed for the first time in this research. The proposed ‎modulator is dedicated to operate with the two major WLAN and GSM standards. It is designed at ‎system level in general, but the VCO part is implemented at transistor level using 180nm CMOS ‎technology. The simulations’ results show a saving of at least 86% of power consumption in the ‎VCO part, in the GSM standard compared to WLAN.‎

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In this paper, a flexible Continuous time (CT) feedforward (FF) quadrature delta sigma modulator (QDSM) with variable bandwidth (BW) is proposed. The modulator BW and center frequency (fc) are variable which can be adjusted with two separate parameters. The modulator signal-to-noise ratio (SNR) will be optimized by these parameters at every center frequency and bandwidth. The modulator BW is changed by varies in the complex coefficients, and the structure of the modulator is no changed.
 The proposed modulator is usable in multi standard receivers as well as in receivers with variable frequency input signal or frequency hopping. The center frequency of this modulator is from 0 to 1/4 fs and its bandwidth can be changed from zero to 1/12 fs.An example of quadrature modulator is designed with the proposed design method at the circuit level. The modulator is simulated for 2MHz and 5MHz bandwidths with a sampling frequency of 64MHz. The SNR for these bandwidths are 76.42dB and 56.59dB, respectively. The FOM has been calculated to be 0.375 and 1.46 (pj / conv), respectively.